14 GALLIUM NITRIDE www.analog.com Issue 3 2026 Power Electronics Europe www.power-mag.com to the same high dv/dt voltage, deskew the timing, subtract one channel from the other, and observe the remaining signal. If the CMRR is adequate, only a small residual voltage should be seen - much less than the actual gate signal. Probe loading is another key factor. Ideally, probing should not affect circuit operation or waveforms. Standard high impedance passive probes have an input impedance of 10MΩ in parallel with 3.9pF to 10pF. In contrast, isolated probes have a lower capacitance (under 2pF) to ground. There are also less common, low impedance (500Ω to 5kΩ) passive probes** that offer low capacitance, which can be helpful in these measurements. Results Figure 5 compares the VG – VSW waveform, captured using the A – B method, to the VTOP_GS measurement from the earlier Figure 3 isolated probe setup (shown as a dashed line). For this test, low impedance passive probes (5kΩ //<2pF) were selected because higher capacitance probes (≥3.9pF) caused a noticeable decrease in VSW’s peak amplitude, indicating probe loading. The gate waveforms are a reasonable match, though the A – B method shows a 2.7V peak-topeak residual common-mode signal - high compared to the 7V peak-to-peak VG – VSW signal. High impedance passive probes showed similar levels of residual commonmode noise, but the measured VG – VSW peaks were 17% to 30% lower, likely due to loading, matching, and response issues. In Figure 6, VG and VSW were captured using a single passive probe in two steps. With this method, the VG waveform is captured and saved in memory. The same probe is then moved and used to capture VSW. Note that a second probe, connected to VSW, triggers the oscilloscope during both measurements. Channel math is used to recall and subtract the waveforms. This approach adds an extra step but improves common-mode rejection by avoiding probe mismatches. While high impedance passive probes performed better than expected, the low impedance probes provided results that more closely matched those of the trusted isolated probe, making them the preferred choice in this case. Conclusion Low voltage GaN DC-to-DC converters offer clear size and performance advantage over their silicon counterparts. However, these benefits come with new challenges, including the need for precise gate voltage control and accurate high-side gate measurements. With the right combination of GaN-optimised controllers and appropriate measurement techniques, these challenges can be addressed - enabling robust, efficient designs without the need for additional circuitry. Analog Devices: www.analog.com Reference 1“Fundamentals of Floating Measurements and Isolated Input Oscilloscopes.” Tektronix. About the Authors Kurk Mathews is a senior applications manager for the Power Control Group at Analog Devices in California. His group supports power applications and the development of new controllers. He enjoys analogue circuit design and troubleshooting using a variety of new and old test equipment. Kurk graduated from the University of Arizona with a B.S. in electrical engineering. Luis Onofre Lazaro is an applications engineer for the Power Control Group at Analog Devices in California. Luis joined ADI after graduating from California Polytechnic State University in 2020 with a B.S. in electrical engineering. Figure 6. TOP FET gate measurement (VG - VSW) using one probe. **Referred to as high frequency, low impedance resistor divider, 50Ω or Z0 probes Figure 5. TOP FET gate measurement (VG – VSW) using A – B method.
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