Power Electronics Europe April/May Issue 2022

InnoGaN patented strain enhancement layer technology which reduces sheet resistance by 66%. Gate charge (QG) is typically 12.7nC. The 5x5 grid wafer level chip scale package (WLCSP) measures just 2x2 mm. In March they announced a new ultra-high-density 140 W power supply demo that uses the company’s high- and low-voltage GaN HEMT devices to achieve efficiencies of over 95 % (230VAC; 5 V/28 A). Measuring just 60x60x22 mm (2.4x2.4x0.9 in) the PSU has a power density of 1.76 W/cm 3 (29 W/in 3 ). The 140 W 300 kHz AC/DC adapter uses a CRM Totem Pole PFC + AHB topology. It features INN650DA140A, a 650 V/140m Ω GaN HEMT in the 5x6 mm DFN package, for switches S1 and S2, the 650 V/240 m Ω , 8x8 mm DFN-packaged INN650D240A for S3, and the INN650DA240A, a 5x6 mm DFN 650 V/240m Ω device for S4. S5 and S6 are delivered by the INN150LA070A, a 150 V/7m Ω , 2.2x3.2 mm LGA part within Innoscience’s low-voltage GaN HEMT range. Commented Dr. Denis Marcon, General Manager of Innoscience Europe and Marketing Manager for the USA and Europe: “GaN technology has been adopted by manufacturers of mobile phone chargers over the last couple of years to deliver increased power and shrink device size. However, Innoscience’s significant breakthrough now makes it possible to introduce GaN HEMTs into mobile phone handsets as well, increasing efficiency and performance. With Innoscience’s huge available capacity, we provide the secure supply chain that customers nowadays expect.” Goal to rank number one by controlling own fabs Thus PEE took the opportunity to ask Denis Marcon about the company’s GaN strategy and manufacuring capability as well as future applications. PEE: GaN on Silicon has been in mass production for almost 12 years with vendors such as EPC, Infineon/Panasonic, GaN Systems, Navitas, Nexperia, PI, STM, TI, or Transphorm. Some of them manufacture GaN power devices in- house, other uses the foundry-model. What differentiates Innoscience from these companies and in particular from world-leading foundries such as TSMC serving many of the mentioned vendors? DM: I think the big difference is the fact that we own and control our own fabs, and this means we don’t have to fight for capacity. In simple terms, if you don’t fight for capacity, you then have stability of supply. We are much, much bigger in terms of capacity– around three times bigger - than the closest player that is a foundry who is serving several fabless players. Furthermore, contrary to everybody else, we produce on eight-inch wafers versus six-inch. This means almost 2x more devices/wafer and thus greater capacity, and lowest price as a result. And that goes hand in hand with the economy of scale. PEE: Innoscience uses 8-inch wafers so far. What is the effect of the company’s stress enhancement layer regarding (dynamic) on-resistance and how does it differentiate from other devices? DM: We do indeed use eight-inch wafers. But actually, the stress enhancement layer has no relation to the wafer size. The stress enhancement layer is proprietary to Innoscience and enables our devices to have a very low dynamic on-resistance measure. The strain enhancement layer technology consists of the deposition of a specific layer after the gate stack definition. The stress modulation created by the strain enhancement layer induces additional piezoelectric polarizations; this causes the 2DEG density to increase and thus the sheet resistance to decrease by 66 % compared with a device without strain layer. Since the strain enhancement layer is deposited after the gate formation, it only affects the resistance in the access region and it does not impact other device parameters such as threshold, leakage etc. The bottom Issue 2 2022 Power Electronics Europe www.power-mag.com 8 MARKET NEWS line is that our devices today have very, very low dynamic on-resistance over the full temperature and voltage range of a given device. PEE: Since 2019 there is a shortage in 8-inch wafer production capacity. Is Innoscience affected by this trend and if yes, how to overcome this shortage? Possibly moving towards 12-inch? DM: It’s important to differentiate between the Silicon <100> that is used by the CMOS industry, and the silicon <111> that is used by the GaN industry. So, that’s the first differentiator. We have agreement in place with our suppliers so we are not affected by this. We have also bought our stock to assure the supply, so we’re good. Regarding an eventual move to 12-inch, that is of course something that we think about. We could produce more wafers, and we could also use 12-inch tools in the future. Let’s say we remain open- minded about that possibility. PEE: According to the website “Innoscience is the largest IDM that is fully focused on GaN technology. This means that Innoscience will fully support you by listening to your needs, providing Innoscience’s samples and devices, developing specific devices for you and, in case of need, we can also support you to develop your system based on Innoscience’s GaN devices.” So, do customers have to follow certain design rules? Do you offer them company- specific devices or even GaN ICs at which quantity? DM: First of all, it’s important to remember we are not a foundry. We don’t provide customers with rigid design rules for them to design with our