Power Electronics Europe February/March 2022

24 INDUSTRY NEWS Issue 1 2022 Power Electronics Europe www.power-mag.com has a Type II staggered band alignment, whereby the valence band maximum in Si 3 N 4 is higher than in GaN. This means holes generated in GaN near the interface have no (or low) barrier for emission into the dielectric. In the final step of this process, holes become trapped in the dielectric, leading to a growing positive charge density Q h . This charge, in turn, leads to an increasing electric field in the dielectric between the metal field plate and gate metal in the vicinity of the gate sidewall. Once this charge density reaches a critical density (Q c ), the dielectric ruptures, leading to the kind of catastrophic damage near the sidewall observed in failure analyses of gate failures. Stress on the drain One common concern among GaN transistor users is dynamic on-resistance. This is a condition whereby the on-resistance of a transistor increases when the device is exposed to high drain-source voltage (V DS ). The traditional way to test for this condition is to apply maximum-rated DC V DS at maximum-rated temperature (typically 150°C). If there are no failures after a certain amount of time – usually 1000 hours – the product is considered good. The dominant mechanism causing the on-resistance to increase is the trapping of electrons in trap-states near the channel. As the trapped charge accumulates, it depletes electrons from the two-dimensional electron gas (2DEG) in the ON state, leading to an increase in R DS(on) . By applying DC V DS at maximum temperature, the electrons available to be trapped come from the drain-source leakage current, IDSS. In order to accelerate trapping, devices can be taken to voltages above their rated maximum. Figure 2 is a magnified image of an EPC2016C GaN transistor showing thermal emissions in the 1–2 m optical range. Emissions in this part of the spectrum are consistent with hot electrons and their location in the device is consistent with the location of the highest electric fields when the device is under drain-source bias. Knowing that hot electrons in this region of the device are the source of trapped electrons, a better understanding of how to minimize the dynamic on- resistance can be achieved with improved designs and processes. By understanding the general behavior of hot electrons, their behavior over a wider range of stress conditions can be generalized. In addition, by providing more hot electrons, the trapping mechanism can be accelerated. To accomplish this, the circuit shown in Figure 3 that pushes high IDSS through the device at maximum rated V DS was created. In other words, instead of just using the leakage current generated by DC bias at high temperatures as the source of electrons that can get trapped, orders of magnitude more trapping candidates can be generated independent of temperature by making a switching circuit such as shown in Figure 3, one of the proposed hard-switching topologies by JEDEC JEP173. Continuous hard switching The resistive hard-switching system was used to test six samples of EPC2218 Figure 3: Hard-switching circuit consistent with JEDEC JEP173 Figure 2: A magnified image of an EPC2212 eGaN FET showing light emissionin the 1–2 m wavelength range (SWIR) that is consistent with hot electrons. The SWIR emission (red- orange) has been overlaid on a regular (visible wavelength) microscope image Figure 4: Long-term dynamic R DS(on) for six samples of EPC2218 eGaN FETs under continuous resistive hard-switching operation for over 1000 hours at ambient temperature and a bias of 100 V. The graph on the top shows R DS(on) versus Time, while the bottom graph shows R DS(on) normalized to its value after the first 10 minutes. Note that even over 1000 hours of operation, R DS(on) does not deviate from a simple log(time) growth dependence