Power Electronics Europe February/March 2022

INDUSTRY NEWS 23 www.power-mag.com Issue 1 2022 Power Electronics Europe GaN devices have been in volume production since 2010 and have demonstrated very high reliability in both laboratory testing and customer applications, such as lidar for autonomous cars, 4G base stations, vehicle headlamps, and satellites to name just a few. Test-to-fail testing can isolate intrinsic failure mechanisms and their behavior over all stress conditions. This information can then be used with confidence to predict device lifetime under a wide range of actual mission profiles. “The release of EPC’s Phase-14 reliability report represents the cumulative experience of millions of devices and five generations of technology to lead to a deeper understanding of the behavior of GaN devices over a wide range of stress conditions,” said Alex Lidow, CEO and co-founder of EPC. Why test-to-fail in addition to standard qualification testing? Standard qualification testing for semiconductors typically involves stressing devices at or near the limits specified in their datasheets for a prolonged period of time, or for a certain number of cycles. The goal of qualification testing is to have zero failures out of a relatively large group of parts tested. This type of testing is inadequate since it only reports parts that passed a very specific test condition. By testing parts to the point of failure, an understanding of the amount of margin between the datasheet limits can be developed, and more importantly, an understanding of the intrinsic failure mechanisms can be found. By knowing the intrinsic failure mechanisms, the root cause of failure, and the behavior of this mechanism over time, Report on GaN Reliability and Physics- Based Models to Project Device Lifetime EPC released recently its Phase-14 Reliability Report, documenting the strategy used to achieve a remarkable field reliability record. The rapid adoption of GaN devices in many diverse applications calls for the continued accumulation of reliability statistics and research into the fundamental physics of failure in GaN devices. The Phase-14 Reliability Report presents the strategy used to measure and predict lifetime based upon tests that force devices to fail under a variety of conditions. temperature, electrical or mechanical stress, the safe operating life of a product can be determined over a more general set of operating conditions As with all power transistors, the key stress conditions involve voltage, current, temperature, and humidity, as well as various mechanical stresses. There are, however, many ways of applying these stress conditions. For example, voltage stress on a GaN FET can be applied from the gate terminal to the source terminal (V GS ), as well as from the drain terminal to the source terminal (V DS ). These stresses can be applied continuously as a DC bias, they can be cycled on-and-off, or they can be applied as high-speed pulses. Current stress can be applied as a continuous DC current, or as a pulsed current. Thermal stresses can be applied continuously by operating devices at a predetermined temperature extreme for a period of time, or temperature can be cycled in a variety of ways. By stressing devices with each of these conditions to the point of generating a significant number of failures, an understanding of the primary intrinsic failure mechanisms for the devices under test can be determined. To generate failures in a reasonable amount of time, the stress conditions typically need to significantly exceed the datasheet limits of the product. Care needs to be taken to make certain the excess stress condition does not induce a failure mechanism that would never be encountered during normal operation. To make certain this is not the case, the failed parts need to be carefully analyzed to determine the root cause of their failure. Only by verifying the root cause can a true understanding of the behavior of a device under a wide range of stress conditions be developed. It should be noted that, as more understanding of intrinsic failure modes in eGaN devices is gained, two facts have become clear; eGaN devices are more robust that Si- based MOSFETs, and MOSFET intrinsic failure models are not valid when predicting eGaN device lifetime under extreme or long-term electrical stress conditions. Physics-Based Derivation of Gate Lifetime Model A host of basic experiments aimed at clarifying the root cause of gate failure were conducted. For the lowest voltage legs, the total stress period exceeded 2000 hours, allowing the generation of more failures and tightened statistical confidence intervals. In addition, the breakdown strength of the of Si3N4 dielectric layer was thoroughly characterized, using dedicated test structures and alternating field direction. Finally, electro-luminescence (EL) studies were conducted on devices to understand the dynamics in time leading up to catastrophic gate rupture. As a result of these collective observations, a multi-step process was theorized to be responsible for gate failure at high V GS . This process is depicted schematically in Figure 1. In the first step, electrons are injected into the pGaN gate layer from the 2DEG. They are injected via tunneling or thermionic emission over the AlGaN hetero-barrier. Once inside the pGaN layer, the electrons gain energy rapidly from the electric field, with some gaining sufficient energy to cause impact ionization. This leads to the generation of electron-hole pairs, particularly in the high field region just under the gate metal. In the second step of this process, holes move away from the gate metal under the influence of the field. Near the sidewall of the gate, a certain fraction of holes scatter into the Si 3 N 4 dielectric, where they become trapped in deep states. This process is aided by the fact that the Si 3 N 4 /GaN interface Figure 1: Schematic of gate failure mechanism in an GaN transistor. A small current of electrons tunneling through the AlGaN front barrier enter the pGaN gate region, where they are accelerated in high fields toward the gate metal. A small percentage gain sufficient energy to cause impact ionization,particularly near the gate metal. The resulting holes are mostly swept away, but some trap and accumulate in the Si 3 N 4 dielectric layer. Once sufficient trapped hole density, Q h , has accumulated, fields concentrate in the dielectric, ultimately leading to catastrophic rupture.