April/May 2021

14 INDUSTRY NEWS a 3.3 V PWM signal is required (DSP, MCU, etc.) an additional buffer can be placed before the PWM input pin (Figure 4) with the buffer supply voltage connected to the V DD capacitor. Drain-to-Source voltage considerations GaN Power ICs have been designed and tested to provide significant design margin to handle transient and continuous voltage conditions that are commonly seen in single-ended topologies, such as quasi-resonant (QR) flyback applications. The different voltage levels and recommended margins in a typical QR flyback can be analyzed using Figure 5. When the device is switched off, the energy stored in the transformer leakage inductance will cause V DS to overshoot to the level of V SPIKE . The clamp circuit should be designed to control the magnitude of V SPIKE . It is recommended to apply an 80 % derating from V DS(TRAN) rating (800V) to 650 V max for repetitive V DS spikes under the worst case steady-state operating conditions. After dissipation of the leakage energy, the device V DS will settle to the level of the bus voltage plus the reflected output voltage which is defined as V PLATEAU . It is recommended to design the system such that V PLATEAU follows a typical derating of 80 % (520 V) from V DS(CONT) (650 V). Finally, VDS(TRAN) (800 V) rating is also provided for events that occur on a non-repetitive basis, such as line surge, lightning strikes, start-up, over-current, short-circuit, load transient, and output voltage transition. 800 V V DS(TRAN) ensures excellent device robustness and no-derating is needed for these non-repetitive events, assuming the surge duration is <100 ms. For half-bridge based topologies (Figure 6), such as LLC, V DS voltage is clamped to the bus voltage. VDS should be designed such that it meets the V PLATEAU derating guideline (520 V). www.navitassemi.com Figure 6: Half-bridge LLC To receive your own copy of Power Electronics Europe subscribe today at: www.power-mag.com VISIT US AT PCIM DIGITAL DAYS Kool Mµ ® Hƒ Powder Cores Lowest Losses for High Frequencies Optimized for 200-500 kHz Edge ® Powder Cores Best DC Bias for Cutting Edge Performance and Compact Design www.mag-inc.com DC Bias (Oe) % Initial Permeability µ i 100% 90% 80% 70% 60% 50% 40% 10 100 200 300 60µ Edge 60µ High Flux Flux Density (Tesla) Core Loss (mW/cm 3 ) 1000 100 10 0.01 0.1 0.3 300 kHz 100 kHz 300 kHz Kool Mµ Hƒ 100 kHz Kool Mµ Hƒ Kool Mµ Kool Mµ