April/May 2021

INDUSTRY NEWS 13 www.power-mag.com Issue 2 2021 Power Electronics Europe above and below the rising and falling input thresholds (4 V and 1 V), the internal gate of the power FET toggles on and off between VDD and 0 V. The drain of the power FET then toggles between the source voltage (typically power ground) and a higher voltage level (650 V max), depending on the external power conversion circuit topology. Programmable turn-on dV/dt control During first start-up pulses or during hard-switching conditions, it is desirable to limit the slew rate (dV/dt) of the drain of the power FET during turn-on. This is as much as possible. To further reduce high-frequency noise, this GaN Power IC includes two Source Kelvin (SK) pins. The SK pins are on-chip kelvin contacts to the Source and are separate from the high current Source connections.The GND connections for components CVDD and DZ should be connected to SK pin, and the GND connection for CVCC should be connected to CP pin 30. SK pin 29 should be left unconnected (N/C). When Figure 3: Current sensing circuit Figure 4: 3.3 V PWM input buffer circuit necessary to reduce EMI or reduce circuit switching noise. To program the turn-on dV/dt rate of the internal power FET, a resistor (R DD ) is placed in between the V DD capacitor and the VDD pin. This resistor (R DD ) sets the turn- on current of the internal gate driver and therefore sets the turn-on falling edge dV/dt rate of the drain of the power FET (Figure 2). Source Kelvin ground pins For high current and hard-switching CCM applications, high-frequency switching noise due to PCB layout parasitic inductance should be minimized using an external gate drive buffer for PWM, the GND of the external gate drive buffer should be connected to the SK pin 29. This will minimize any possible high frequency voltage spikes from occurring at the PWM input during switching. Current sensing For many applications it is necessary to sense the cycle-by-cycle current flowing through the power FET. To sense the current flowing through the GaNFast power IC, a standard current-sensing resistor can be placed in between the source and power ground (Figure 3). In this configuration, all of the components around the GaNFast power IC (C VCC , C VDD , DZ, etc.) should be grounded with a single connection at the source. Also, an additional RC filter can be inserted between the PWM signal and the PWM pin (100 Ω , 100 pF typical). This filter is necessary to prevent false triggering due to high- frequency voltage spikes occurring at the source node due to external parasitic inductance from the source PCB trace or the current- sensing resistor itself. For increased cooling pad PCB copper area it may be desired to connect CP to the circuit PGND. Figure 3 shows the components around the GaNFast power IC grounded at the source pins (S) and CP connected to PGND. This allows for all CP pins and CP pad to be connected to a large and continuous thermal copper area without being obstructed by the current sensing resistor. For some applications where RIGHT Figure 5: QR flyback drain-to- source voltage stress diagram