February/March 2021

16 INDUSTRY NEWS Issue 1 2021 Power Electronics Europe www.power-mag.com the cumulative failure probability for different stress conditions applied to the gate. The plot on the left has different voltages at room temperature and the plot on the right shows two different voltages applied at 120°C. This device has a datasheet maximum gate voltage rating of 6 V, yet very few devices are failing even after many hours at 8 V. In Figure 2 these data have been translated into failure rates. On the left is the mean time to failure (MTTF) for these same devices vs V GS at both 25°C and 120°C. On the right is a graph that shows the various probabilities of failure versus V GS at 25°C. The failure rate is not very sensitive to temperature but is very sensitive to V GS . Looking at the graph on the right, with a V GS of 6 V DC, which is the absolute maximum allowed voltage for this part one could expect between 10 and 100 parts per million (ppm) failures in 10 years. The recommended gate drive voltage, however, is 5.25 V and the expected failure rate at that voltage is less than 1 ppm in 10 years. These conclusions are only valid if the primary failure mechanism is the same under all these conditions. In order to confirm this, failure analysis was performed on multiple parts from this study, and a consistent failure mode was found. Referring to the image in Figure 3, the yellow circle indicates the failure site is between the gate metal and the metal 1 layer. These two layers are separated by a Silicon Nitride dielectric layer. It is this layer that failed, not any of the GaN layers beneath. While this lifetime study provided a solid phenomenological model of gate reliability in eGaN FETs, many fundamental questions remained unanswered:  Is the exponential scaling of MTTF with gate voltage truly applicable to eGaN FETs? Is there perhaps a different mathematical model that is predicated on the root physics of failure in GaN?  Why does dielectric rupture occur in a high- quality silicon nitride film at an electric field well below its breakdown strength? And, why does this rupture occur at the corner of the gate?  Why does gate lifetime increase as temperature rises? To resolve these questions, EPC conducted more extensive gate acceleration studies on recent lots of EPC2212 devices, using larger sample sizes and longer durations (> 1000 hours in some cases). In addition, several core experiments to uncover the dynamics of failure at high gate bias were performed. These studies resulted in an improved understanding of the physics of failure and, for the first time, a lifetime equation specific to eGaN technology that is derived directly from this physics. EPC has gathered convincing evidence that gate failure at high bias in eGaN FETs is caused by a two-step process. In the first step, impact ionization inside the p-GaN gate layer leads to the production of electron-hole pairs. Some of these holes scatter and trap in the Si3N4 layer near the corner(s) of the gate. Over time, as this trapped hole charge density accumulates, the electric fields in the dielectric grow until, at a certain critical charge density, it ruptures catastrophically. Figure 4 shows the lifetime model plotted against the measured MTTF of an EPC2212 eGaN FET from a recent acceleration study. In contrast with the simple exponential model, the new equation bends upward at low gate bias, resulting in an increased life expectancy when the devices are operated within their datasheet range (< 6 V). In addition, the new model provides a better fit to measurement, wherein the voltage acceleration is observed to decrease as VGS rises. Figure 5 shows the temperature dependence of the lifetime equation at ?75°C, 25°C, and 125°C. At higher temperature the MTTF is slightly higher, as observed in the measurements shown in Figure 2. Safe Operating Area Testing Safe operating area (SOA) testing exposes the eGaN FET to simultaneous high current (I D ) and high voltage (V DS ) for a specified pulse duration. The primary purpose is to verify the FET can be operated without failure at every point (I D , V DS ) within the datasheet SOA graph. It is also used to probe the safety margins by testing to fail outside the safe zone. During SOA tests, the high-power dissipation Figure 2: Mean time to failure (MTTF) for EPC2212 eGaN FETs (left) versus V GS at both 25°C and 120°C. Various probabilities of failure versus V GS at 25°C (right) Figure 3: Scanning electron microscopy (SEM) image of the gate region of an EPC2212 eGaN FET. The yellow circle shows the failure site is between the gate metal and the metal 1 layer