February/March 2021

INDUSTRY NEWS 15 www.power-mag.com Issue 1 2021 Power Electronics Europe This Phase 12 reliability report adds to the extensive knowledge base published in the first eleven reports. It details how by employing a test to fail methodology, intrinsic failure mechanisms can be identified and used to develop physics- based models to accurately project the safe operating life of a product over a more general set of operating conditions. This methodology is also employed to consistently produce more robust, higher performance, and lower cost products for power conversion applications. Test-to-fail vs qualification testing Standard qualification testing for semiconductors typically involves stressing devices at or near the limits specified in their datasheets for a prolonged period of time, or for a certain number of cycles. The goal of qualification testing is to have zero failures out of a relatively large group of parts tested. This type of testing is inadequate since it only reports parts that passed a very specific test condition. By testing parts to the point of failure, an understanding of the amount of margin between the datasheet limits can be developed, and more importantly, an understanding of the intrinsic failure mechanisms can be found. By knowing the intrinsic failure mechanisms, the root cause of failure, and the behavior of the device over time, temperature, electrical or mechanical stress, the safe operating life of a product can be determined over a more general set of operating conditions. As with all power transistors, the key stress conditions involve voltage, current, temperature, and humidity, as well as various mechanical stresses. There are, however, many ways of applying these stress conditions. For example, voltage stress on a GaN FET can be applied from the gate terminal to the source terminal (V GS ), as well as from the drain terminal to the source terminal (V DS ). These stresses can be applied continuously as a DC bias, they can be cycled on- and-off, or they can be applied as high-speed pulses. Current stress can be applied as a continuous DC current, or as a pulsed current. Thermal stresses can be applied continuously by operating devices at a predetermined temperature extreme for a period of time, or temperature can be cycled in a variety of ways. By stressing devices with each of these conditions to the point of generating a significant number of failures, an understanding of the primary intrinsic failure mechanisms for the devices under test can be determined. To generate failures in a reasonable amount of time, the stress conditions typically need to significantly exceed the datasheet limits of the product. Care needs to be taken to make certain the excess stress condition does not induce a failure mechanism that would never be encountered during normal operation. To make certain this is not the case, the failed parts need to be carefully analyzed to determine the root cause of their failure. Only by verifying the root cause can a true understanding of the behavior of a device under a wide range of stress conditions be developed. It should be noted that, as more understanding of intrinsic failure modes in eGaN devices is gained, two facts have become clear; (1) eGaN devices are more robust that Si-based MOSFETs, and (2) MOSFET intrinsic failure models are not valid when predicting eGaN device lifetime under extreme or long-term electrical stress conditions. Stress on the Gate Figure 1 is an example of a Weibull plot of gate failures in an EPC2212 FET. The horizontal axis shows the time to failure. The vertical axis shows EPC eGaN Gate Acceleration Reliability Testing eGaN devices have been in volume production for more than a decade and have demonstrated very high reliability in both laboratory testing and customer applications. Field reliability data over a period of four years and 226 billion hours of operation, most of which are on vehicles or used in telecommunication base stations, demonstrate a robustness that is unmatched by silicon power devices. EPC developed a custom system to assess eGaN reliability over long-term ultra-high dv/dt and di/dt pulse stress conditions such as might be encountered in automotive lidar systems. As of January 2021, devices have passed thirteen trillion pulses (about triple a typical automotive lifetime) without failure or significant parametric drift. Figure 1: Weibull plots of gate-to- source failures of EPC2212. Very few failures occur even at 8 V GS , yet the device has a maximum V GS rating of 6 V. The data on the top is at 25°C and the data on the bottom is at 120°C