22 POWER MODULES https://www.analog.com/en/index.html Issue 2 2024 Power Electronics Europe www.power-mag.com How to Optimise a Second-Order Output Filter for an Ultralow Noise µModule Regulator George (Zhijun) Qian, Senior Analog Design Engineering Manager, and Jennifer Florence Joseph Benedicto, Senior Design Evaluation Engineer, Analog Devices Question Can we further reduce the output switching noise of an ultralow noise µModule® regulator? Answer The output noise of an ultralow noise µModule regulator can be reduced by over 90% using a second-order output filter. Proper care must be taken to select the capacitor and inductor components to maintain fast and stable control loop. This design is particularly beneficial for wireless and RF applications, where a fast transient response minimises system blanking time and maximises signal processing efficiency. This methodology achieves noise levels comparable to an LDO with the efficiency of a switching regulator. Introduction Power consumption for noise sensitive devices is increasingly growing. Applications such as medical ultrasound imaging systems, 5G transceivers, and automatic test equipment (ATE) demand high output current (>5A) with a low noise level and high bandwidth in a small PCB area. Due to the high output current demand, the traditional two stage (buck + low dropout (LDO) regulator) solution that was previously used requires more PCB area and incurs more power loss, making it less preferred. The LTM4702 ultralow noise µModule regulator features Analog Devices’ proprietary Silent Switcher® technology, an ultrafast transient response, and ultralow noise architecture. All these features make it ideal for high current and noise-sensitive applications, while still maintaining the high efficiency of a synchronous switching regulator. This solution could eliminate LDO circuitry for many applications, which saves LDO cost (~60%), LDO power loss (4W and up), and LDO PCB space (2cm2 + clearance). For certain applications requiring a very small switching frequency ripple, it is well known that a second-order LC filter can reduce the switching frequency harmonics of the output voltage. However, the design challenge is minimising the switching ripple while still maintaining a stable control loop with high control loop bandwidth. Often, the control loop becomes unstable after adding an unoptimised LC filter, which causes the output to oscillate. In this article, a simplified loop analysis of the secondorder LC filter is first discussed, and then an intuitive design method is given to guide on capacitance distribution and inductance calculation. Lastly, the LTM4702 design example verifies the proposed design method. Figure 1. A current-mode buck regulator along with a second-order LC and its typical Bode plot. Loop Analysis of a Second-Order LC Output Filter Design In a current-mode buck regulator, the output impedance is the control plant. Figure 1 shows the circuitry of a second-order LC and its typical Bode plot. To maintain accurate DC voltage regulation at load, VOUT remote node B is sensed. The transfer function from VOUT to iLO is:
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