14 POWER SUPPLY DESIGN www.analog.com Issue 1 2024 Power Electronics Europe www.power-mag.com power supply voltage in different scenarios. There are voltage transients that can occur in a system that are not associated with the power supply voltage but rather on a user interface such as a mechanical switch or a conductive card for some applications. Turning a switch on and off produces voltage transients and noise on the input pin, typically a manual reset pin. Power supply noise, voltage transients, and glitches, if excessive, can unintentionally hit the under-voltage or over-voltage threshold of a supervisor and trigger false resets if not accounted for in the design. This can lead to oscillatory behaviour and instability, which is undesirable with regards to system reliability. Noise and transients There are parameters that help mask these transients that are associated with the power supply or monitored voltage. These are the reset timeout period, reset threshold hysteresis, and the reset threshold overdrive versus duration. The transients that are associated with the mechanical contact in the circuit such as a pushbutton switch in the manual reset pin, the manual reset setup period and the debounce time mask the transients. These parameters make the voltage supervisors robust and unaffected by transients and glitches, thus keeping the system from undesirable responses. Reset timeout period (tRP) During startup or when the supply voltage is rising up from an under-voltage event and exceeds the threshold, there is an additional time on the reset signal before it de-asserts, which is called the reset timeout period (tRP). For example, Figure 3 shows that after the monitored voltage, which in this case is the supply voltage labeled as VCC, reaches the threshold from an under-voltage or startup, an added delay is present for an active LOW reset before it de-asserts ‘high’. This additional time gives room for the monitored voltage to stabilise first, masking the over-shoot and ringing before enabling the system or taking it out of reset mode. The reset timeout period suppresses false system resets to prevent oscillation and potential malfunction, thus helping improve the reliability of the system. Threshold hysteresis (VTH+) There are two main benefits of having threshold hysteresis. First, it provides certainty that the monitored voltage has overcome the threshold level with enough margin before de-asserting a reset. Second, it gives room for the power supply to stabilise first before de-asserting a reset. There is a tendency for the reset output to produce multiple transitions when processing signals with superimposed noise, as the power supply bounces and recrosses the threshold region. This is shown in Figure 4. In applications such as industrial environments, noisy signals and voltage fluctuations can occur anytime. Without hysteresis, the reset output will continuously toggle assert and de-assert until the power supply stabilises. It will also put the system into oscillation. Threshold hysteresis cures the oscillation by putting the system hold on reset to prevent the system from unwanted behaviour shown in the blue-shaded area in Figure 4. This helps the supervisor in protecting the system from false resets. Voltage glitches from external factors can occur in any system for either short or long periods. They can also have different magnitudes of voltage dip. Reset threshold overdrive versus transient duration has something to do with the magnitude and duration of the voltage glitch or overdrive. A short-duration glitch with a greater magnitude will not trigger a reset signal to assert, while a less-magnitude overdrive with a longer duration will trigger a reset as shown in Figure 5. Voltage transients in the monitored supply are ignored depending on the duration. Disregarding these transients will protect a system from nuisance resets such as those caused by short-duration glitches. These glitches can falsely trigger system resets, to undesirable behaviour of the system. In the product data sheet, the reset threshold overdrive vs. duration is often illustrated in one of the typical performance characteristics plots such as Figure 3: The reset timeout period (tRP) helps keep the system in reset mode while the supply voltage stabilises. Figure 4: Reset output response without and with threshold hysteresis (reset timeout period not shown to focus on the effect of hysteresis).
RkJQdWJsaXNoZXIy MjQ0NzM=