www.empowersemi.com POWER CAPACITORS 21 www.power-mag.com Issue 4 2023 Power Electronics Europe Silicon capacitors are relatively new, created by vertical trenches in silicon using an ultra-fine lithography process. This allows many capacitors to be formed in a very small space where electrodes are orders of magnitude shorter than MLCCs, providing the same order of magnitude reduction in ESL. A large number of such capacitor cells (100s or 1000s) are connected in parallel to form a single capacitor further reducing effective ESL. Standard metal layers available in siliconbased semiconductor processes can connect to the electrodes anywhere on the silicon die, enabling termination flexibility and performance. Using silicon-based semiconductor processes also provides an inherent stability against variations in voltage, temperature and ageing that MLCCs struggle with, resulting in a much more stable and reliable product. There is an immediate density improvement for silicon capacitors compared to MLCCs for the same effective capacitance and decoupling requirements. Empower’s E-CAP silicon capacitor portfolio, for example, features a single capacitor of 220nF that fits standard 0201 footprints, up to an array of 17 single capacitors (4,800nF) in a single, low profile, surface mount, chip scale package (Figure 1). The combined impact of an MLCC’s ageing and de-rating factors is illustrated in Figure 2. The table in Figure 2 showcases a 54nF E-CAP compared to an example 100nF MLCC. The effective capacitance achieves the required 44nF, but the E-CAP achieves this with only the initial tolerance specification added. It is also more resistant to ageing. In this example, double the number of MLCCs would be required, effecting board space and layout. Impedance versus frequency Figure 3 illustrates how the low ESL attributes of an E-CAP offer high frequency impedance characteristics above 50MHz. For example, an average MLCC may have an ESL of 200pH compared to an E-CAP’s 15pH. Even a commonly used network of MLCCs with reducing values and case sizes features more than two times the impedance at many 100s of MHz than a solution using E-CAPs which uses 40% fewer components. An examination of the physical placement of capacitors is warranted to ensure their effective utilisation. When series inductances in the order of pH start to make an impact on the de-coupling capability, the inductance of the traces connecting the capacitors to their decoupling points start to feature the same order of magnitude as the capacitor’s ESL. Placing such capacitors too far away will render them useless and the benefits versus MLCCs may not be apparent. High performance processors are typically mounted as die on silicon substrates that are then moulded over to form a package. The packages house multiple die, i.e., the processor, memory, communications chips, as well fan out the fine pitch of the die (e.g., 150µm) made in deep sub-micron processes to a manageable I/O pitch for PCB mounting (e.g., 500µm). There are multiple levels of Figure 3: Impedance versus frequency curves comparison of MLCCs and E-CAPs. (Source: Empower) Figure 4: E-CAP mounting locations.
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