18 POWER CAPACITORS www.empowersemi.com Issue 4 2023 Power Electronics Europe www.power-mag.com Emerging high frequency, high power applications need a rethink on capacitors to maintain power integrity There is an alternative to using traditional multi-layer ceramic capacitors (MLCCs) to fulfill high frequency power demands in IoT devices, mobile phones and high performance computing applications. By Mukund Krishna, Senior Manager, Product Marketing and Luca Vassalli, Customer Applications Engineering Director, Empower Semiconductor As one of the most fundamental components in electronics, capacitors are used in large numbers across a variety of designs to maintain power integrity. They are a key requirement for applications such as mobile phones, IoT devices and HPC (high performance computing) applications and address last mile power delivery challenges, such as high frequency power demands for the high performance processors. While traditional MLCCs have fulfilled the requirements thus far, stricter constraints on power density are challenging the continued usage of the existing model. As system engineers look to deliver the promised and expected performance in smaller form factors, provision of the most efficient power de-coupling solution is a critical design consideration. It is currently estimated that over one trillion capacitors are produced every year, of which 800 billion are surface mount MLCCs or chip capacitors. These are used to address requirements across the complete power and voltage range in applications, including energy storage, filtering and decoupling of power rails to filter out unwanted ripple and noise. The exponential growth in the creation of HPC has been led by the rapid advent of artificial intelligence and machine learning (AI and ML). The magnitude and frequency of instantaneous power demands are growing in steps of 100% for subsequent generations, placing stress on power integrity solutions. When it comes to the latest dataintensive systems built around high performance, high speed processors and multiple power domains that operate with fast transients and low voltages, designers are finding a growing number of challenges with conventional MLCC capacitors. These processors are increasingly used on highly dynamic workloads, such as running AI algorithms and neural network models for ML and inference. For such applications, the peak current swings become significant, with instantaneous peak processor currents of 800A to 1000A in tens of nanoseconds becoming the norm. This results in extremely challenging current transients (di/dt). These highperformance devices usually require multiple low voltage (0.4V DC to 1.0V DC) power rails and tight adherence to voltage regulation specifications, typically within ±1.0%. Board-mounted switching DC/DC converters offer a viable method of provisioning high power direct to computational devices such as FPGAs, GPUs, and neural network processors (NPUs). While the DC/DC converters mounted on the PCB provide adequate DC power to these workloads, their frequency of operation, and hence bandwidth (which is the ability to respond to ultra-fast current transients), is orders of magnitude lower than required. The sheer volume of such solutions render them being located at distances far enough away that any ability to service fast transients is rendered useless by the high impedance to the processor. The electrical noise generated from transients, power supply ripple and other noise artefacts can significantly impact the performance of the computational ICs and other circuit functions. Signal integrity is tightly associated with power integrity in any complex application, and such artefacts can create ‘ringing’ oscillations across the whole system. Digital processors made with advanced process nodes such as 5nm have extremely tight tolerances on voltage supply to avoid brown-out at the lower end and overvoltage at the upper end. Analogue ICs used in data conversion signal chains are particularly vulnerable to PDN (power delivery network) noise, with its power supply rejection ratio as a critical indicator of susceptibility. As any analogue IC’s datasheet will highlight, small variations of supply voltage can upset the function’s operation. For example, the introduction of jitter on clock signals or the reduction of analogue conversion accuracy. Decoupling power rails Minimising transient, ripple and noise artefacts from the PDN in high frequency, high performance applications is paramount. To decoupe PDN noise artefacts, multiple capacitors, typically MLCCs of different values and case sizes, are placed across the supply rails. The aim is to provide a low impedance return path across a wide frequency range. To provide the most effective noise cancellation, the capacitors are placed closest to the noise sources and the power pins of sensitive ICs. Board layout will influence MLCC placement, but this situation is exacerbated by larger processor ICs requiring tens of capacitors. At higher switching and computational frequencies, PCB trace parasitics and the equivalent circuit characteristics of the MLCCs also become significant. As high frequency processing
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