Power Electronics Europe Issue 4 - November 2022

8 GATE DRIVERS https://www.allegromicro.com/en/ Issue 4 2022 Power Electronics Europe www.power-mag.com and correct choice of gate resistor. The Allegro AHV85110 driver has independent pull-up and pull-down outputs, allowing independent choice of both resistors. A popular method to further mitigate the effects of a false power-on event is through use of a bipolar output drive. Here, a suitable choice of driver supply voltage and Zener diode generates a voltage to prevent the false power-on event. In any electronic circuit, there are many parasitic components that do not appear on the schematic. FET and IC bond wires and packaging along with PCB traces result in unwanted parasitic inductances. FET internal structures and overlapping PCB traces and power planes add circuit node capacitances. In most cases, these parasitic components have little or no impact on circuit performance. However, in power- switching circuits, they can have a severe effect and should be carefully considered. The internal structure, packaging, and pinout of the AHV85110 gate driver have been optimized to minimize such parasitics. The most effective way to reduce the external circuit parasitics is through good PCB layout. The AHV85110 driver pinout easily facilitates the bipolar drive circuit without compromising on the key PCB layout guidelines. PCB layout Increasing the switching frequency can help to reduce the size of the magnet used in the power system, and it is now common to see switching frequencies greater than 500 kHz and even beyond 1 MHz in higher-power converter applications. This increase is further supported by the introduction of high- power, low R DS(ON) and low gate capacitance MOSFETs and GaN FETs. The gate driver also needs to maximize the effectiveness of these FET switches. Faster switching edges both in the gate drive loop and the commutation loop are a continuous design challenge and the effects of PCB parasitic parameters can play a significant role in circuit operation. PCB tracking and layout are fundamental parts of the operation of an electronic circuit. The PCB tracks introduce inductances and capacitances into the circuit, which can often be overlooked. In power-switching circuits, these parasitic components can introduce voltage and current ringing on circuit nodes, which can greatly inhibit circuit performance and introduce undesired effects such as poor circuit operation and increased electromagnetic interference (EMI). A solution is often to add, after the fact, components such as snubbers and filters. A better approach is to eliminate or minimize the effects through good PCB layout practices. Allegro drivers have the unique advantage in that they require the minimum of external components, particularly on the output side, which is the most critical from a PCB layout point of view. The drivers do not require a separate isolated or bootstrap diode—all of that functionality is included in the drivers using the Power-Thru technology. The pinout of the device has been carefully designed for ease of PCB layout and optimal performance. The 12-pin, low- profile, surface-mount package (Allegro part number suffix LH) measures 10 mm 7.66 mm 2.53 mm. Several protection features are integrated, including undervoltage lockout on primary and secondary bias rails, internal pull-down on IN pin and OUTPD pin, fast response- enable input, and OUT pulse synchronization with first IN rising edge after enable, which avoids asynchronous pulses. Good quality decoupling capacitors should be used for decoupling the primary, V DRV , and secondary, CSEC, voltages, and the pinout of gate drivers such as the AHV85110 has been designed for the optimal positioning of these capacitors. The FET drive on pin (OUTPU pin) and the FET drive off pin (OUTPD pin) can be implemented with direct connection to the FET gate or with series resistors to control the FET rise and fall times. Having these functions separated but adjacent on the module allows for independent control of the power-on and power-off times without the need for external parallel diode or transistor circuits, while still allowing the driver to be as close as possible to the driven FET. The gate drive current return to the module is through the OUTSS pins, which are positioned to minimize the loop area for the gate current. An example PCB layout is shown for the AHV85110 used with a commercially available GaN FET and following the recommended layout for the FET. The ever-increasing switching frequencies of power converters results in faster voltage and current transition edges—higher dv/dt and di/dt. This higher-frequency operation, reduced dead time, and sharper switching edges means EMI considerations are also increasingly important yet are often the last considerations in a system design, which can make finishing a design difficult and time consuming. The reduction of components and circuits in and around the gate drive design helps dramatically reduce the EMI challenge in a system design through lower common-mode capacitance (Ccm). This reduces the circulating currents, reducing any EMI and reducing test time. Good PCB layout practices can significantly reduce second-order effects, such as EMI, and can reduce or eliminate Figure 3: Avoiding false power-on events in a gate driver design.