Power Electronics Europe Issue 4 - November 2022

https://www.allegromicro.com/en/ GATE DRIVERS 7 www.power-mag.com Issue 4 2022 Power Electronics Europe the power-module semiconductor switches using external DC-DC bias supplies. These designs are both complex and high in component count, and some require as many as eight or nine separate bias supplies, which typically include transformers and other bulky components. In addition to the added cost, size, and weight that come with these bias supplies, the added component count and circuit complexity affect reliability. Even in designs where care has been taken to minimize the loading and stress on components, every component remains a potential point of failure. The bias supplies included in conventional designs add potential points of failure and must also be sized for the highest operational switching frequency, which results in less-efficient operation at lower frequencies. ELIMINATING THE BIAS SUPPLY Power-conversion technologies that require fewer components than conventional technologies have fewer points of failure, which directly improves reliability and leads to fewer potential warranty claims and enhanced product reputation. One new approach to transfer power to gate drivers, is to use a novel magnetic coupling device within the integrated circuit to eliminate the need for bias supplies, which is what the Power-Thru technology from Allegro MicroSystems does: It transfers the gate on/off logic signal with the power needed to drive the gate of the switch, eliminating the need for external auxiliary power. The reduced component count and complexity cuts engineering time by making modules much easier to design and to qualify. This also allows the gate driver to track the power consumption of the gate control with the switching frequency, enabling automatic optimization of efficiency. This technology reduces the size and weight of the gate driver and brings additional benefits. Smaller gate driver assemblies enable shorter signal paths with reduced parasitic capacitance and inductance, which reduces the risk of damage caused by ringing and voltage spikes. Smaller gate drivers also leave more space for the power stages, enabling the use of more-efficient designs. The Power-Thru technology also removes the need for a bootstrap circuit to create the floating voltage required for controlling the high-side switches. This, in turn, eliminates all the trade-offs and complexity in choosing the optimal combination of components to use in this bootstrap circuit. The Power-Thru technology consists of a tiny magnetic-based isolation structure that enables efficient power transfer across the boundary from the low-voltage signal to the high-voltage system. This boundary carries not only the gate drive signal information but also all the drive power required to drive the external FET switch. The magnetic coupling provides complete electrical isolation, so Power-Thru drivers are equally suitable for use in high-side, low-side, and isolated applications. By eliminating the need for auxiliary power supplies, the Power-Thru gate drivers can free up time to concentrate on core design challenges. In one example, nine separate bias rails were able to be merged into a single rail. The reduced component count can reduce BOM costs, system size, and build complexity. This reduced complexity can improve the likelihood of early success in testing and validation and can increase reliability in application as there are less parts that might fail. The Power-Thru gate drivers also only require a single capacitor to be specified, which speeds design time and improves the likelihood of early design success. Gate driver operation For power-on, it is more important to think in terms of charge transfer than simply charging the input capacitance, C ISS , of the FET. FET capacitances are also highly nonlinear, and the capacitance depends largely on the FET V DS . The high rate of change of voltages and currents in power-switching circuits can create inductor currents and capacitor voltage drops. One example is the false power-on of a FET due to a dv/dt event. For example, after the power-off of the low-side FET and the elapse of a suitable dead time, power-on of the high-side FET occurs. This produces a rapidly changing switch-node voltage at the drain of the low-side FET. The resulting capacitor current flowing in the gate-drain capacitance, CGD, and driver output cause the voltage on the gate of the low-side FET to rise. If this voltage spike peaks beyond the threshold voltage, V TH , the FET will conduct. Because the high-side FET is also conducting, a potentially destructive shoot- through event can result. As the typical FET capacitors are highly nonlinear and a function of V DS , the effect of iCGD gate drive current can be more pronounced at lower values of V DS . This inevitable iCGD current must be managed correctly and emphasizes the importance of a strong driver pull down Figure 2: A typical half-bridge application that uses the Allegro MicroSystems AHV85110 gate driver with Power-Thru technology and eliminates the high- side bootstrap.