October / November 2021

28 GATE DRIVERS www.talema.com Issue 4 2021 Power Electronics Europe www.power-mag.com provide the reset voltage (negative bias) for the magnetizing inductance, preventing transformer saturation. The amplitude of output voltage reduces with the duty ratio increase, hence this circuit limits the duty cycle to less than 50 %. This approach works well in SMPS circuits, where the frequency is high and the duty cycle ratio is small. Gate drive voltage, V c , changes with duty ratio. Sudden changes in duty ratio will excite the L-C resonant tank formed by L m & C, an effect that can be damped by the low value resistor (R). The gate is driven between -V c and V DRV -V c levels as opposed to original output voltage range of the driver, 0 V and V DRV . A back to back Zener diode is used to clamp the device gate voltage, and gate resistor R g is used to avoid gate transient surge current Core saturation limits the applied volt- time product across the windings, and the design must accommodate the maximum volt-time product. The GDT is driven by a variable pulse width as a function of the PWM duty ratio. Amplitude may be constant or variable according to configuration. Single ended and double ended circuits All GDTs operate in both the first and third quadrant of the B-H plane. Single ended gate drive circuits are used with a single output PWM controller to drive a high side switch. The GDT is driven by a variable pulse width and variable amplitude (Figure 6). This circuit is limited to 50 % duty ratio. For wide duty cycle applications, a DC restoration circuit on the Figure 5: Basic circuit of a transformer based isolated gate drive Figure 6: Single ended transformer-coupled gate drive LEFT Figure 7: Double ended transformer- coupled gate drives