October / November 2021

24 POWER SEMICONDUCTORS www.unitedsic.com Issue 4 2021 Power Electronics Europe www.power-mag.com around 1.7 V with 850 W dissipation, equivalent to a MOSFET with 3.4 m Ω on- resistance, which is not available from single devices rated at 400 V and higher. Paralleled MOSFETs reduce dissipation, but ten plus would be needed to match an IGBT in this scenario and if bi-directional conduction is required, as would be typical in an EV application, the number doubles anyway and costs spiral. Table 1 summarizes the relative performance attributes of mechanical and solid-state circuit breakers. A new technology for SSCBs Wide band-gap semiconductors such as Silicon Carbide types (SiC) usually hit the headlines for their fast switching speed, but they also have inherently around 10x better on-resistance for a given die area and voltage rating than Silicon. This makes them potential candidates for small, efficient SSCB switches, and the high material operating temperature and better thermal conductivity are additional benefits for peak power dissipation considerations. Although SiC MOSFETs are most common, the simpler JFET construction (Figure 1, left) can be preferred in the SSCB application with its better on- resistance, R DS(ON) . The device is normally- on with no gate drive but this is often a better characteristic for SSCBs, defaulting to the conducting state with no bias voltages present. Another arrangement is the SiC FET (Figure 1, middle). This device is a ‘cascode’ combination of a SiC JFET and a Silicon MOSFET which is normally- off, with a simple 0-12 V gate drive. On- resistance is 5-15 % higher than the SiC JFET on its own though, for the same voltage and current class of device. A new device has now appeared, the ‘Dual Gate FET’ or DG-FET (Figure 1, right) which is the SiC FET cascode with its two gates uncommitted and brought out to separate pins. The advantage is that the gate drive voltages can now be ‘fine-tuned’ for the absolute minimum on-resistance, typically by driving the JFET gate a little positive in voltage. The Silicon MOSFET gate then acts just as an ‘enable’ signal. The two die are ‘stacked’ for minimum connection distance and losses. Temperature sensing with a DG-FET When the gate of the JFET In a SiC DG-FET is taken positive, at around 2 V, a diode action appears and current flows. If the current is accurately limited to say 1 mA, the voltage at the gate has a direct relationship to the die temperature, so can be used as a sense for over-temperature protection or even long- term state-of-health monitoring. This is a valuable feature in SSCB applications to detect any long-term degradation of cooling efficiency, for example, as the DG-FET may have continuous high current passing and significant dissipation. The effectiveness of current sharing in parallel device can also be monitored by evaluating differences in die temperature. Figure 2 shows the typical relationship between die temperature and SiC JFET gate-source voltage. SSCBs with SiC DG-FETs Figure 3 shows a practical circuit using SiC DG-FETs for a bi-directional SSCB. Gate resistors slow switching to avoid EMI and instability, and the snubber network helps prevent damaging voltage overshoot on switch-off. The MOV also clamps voltage transients induced by line inductance between the DC source and load during switching. Although the DG-FETs do have a robust avalanche rating, it can be beneficial to employ an MOV to absorb the energy stored in the line inductance between source and load, since this can become quite large. A large energy MOV is going to cost a lot less than a SiC FET with the same energy rating in avalanche. With this technique, the cost of the SiC used can be reduced. In fact, using a MOV that better limits peak voltage, lower voltage rating SiC devices can be used, which in turn reduces on-state resistance and cost. To take our example of requiring 3 m Ω devices to be equivalent to a current IGBT, for a uni-directional SSCB, one UG3SC120002SNS device from UnitedSiC could be used, which contains six paralleled 9 m Ω FETs, achieving 2.2 m Ω Figure 2: SiC JFET gate-source voltage scales with die temperature at fixed current Figure 3: DG-FETs as a bi-directional solid-state circuit breaker