October / November 2021

20 EPE ECCE 2021 REVIEW www.epe2021.com Issue 4 2021 Power Electronics Europe www.power-mag.com especially for more than two devices in series- connection. Quasi-two-level (Q2L) modulation of multi-level converter gains increasing attention for medium voltage applications recently, mainly because it has several benefits comparing to both traditional multi-level converter and two- level converter with series-connected devices by reducing conduction time of intermediate voltage level. The Q2L modulation for NPC 3L converter is analyzed to be a better solution comparing to series-connected of 10 kV SiC MOSFETs. By using the zero voltage stage for the short transient period, the voltage balancing of series-connected SiC MOSFETs is avoided. With the Q2L modulation, diodes with smaller volume and no heatsink can be selected as the clamping diodesreduce the cost and improve the power density of the power stage. In the meantime, comparing to3L converter, the NPC 3L converter is more suitable for Q2L modulation with the benefit from switching loss of main devices, the volume of extra components, and fault protection. level (2L) converter with series-connected devices are still required for most of the medium voltage applications. Three-level topologies have better efficiency and no voltage balancing issue for series-connected devices but usually require more semiconductor devices or passive components. On the other hand, the 2L converter with series- connected MOSFETs requires less semiconductors but requires voltage balancing control to avoid device damage. For the fast switching SiC MOSFETs, the voltage balancing becomes more complicated Parasitic turn-on in SiC power modules Parasitic turn on (PTO) in multichip SiC power modules can be substantially different and more complex than in single chip or discrete components. This paper “Assessing the Presence of Parasitic Turn On in SiC Mosfet Power Modules” by Danfoss Silicon Power (http://powermodules.danfoss.com ) proposes a careful extension of the classical double pulse tests, introduce new quantitative MOSFET and Body Diode metrics, and combine these with static characterization data, in order for the user to decide whether a given SiC power module when driven with a certain gate driver scheme experiences PTO or not. Since PTO is a parasitic effect, to uncover its origins in a module we need to figure out all possible coupling mechanisms from an interference source, to the gate-source voltage of the victim chips. At the switching speeds which present day SiC devices operate three main coupling paths can exist - capacitive coupling, conducted coupling and magnetic coupling. To ascertain PTO in a multichip-module-driver system the user should check the second and first turn on pulse in a DP test. Moreover, this should be done quantitatively sweeping the whole voltage, current temperature operating range, while computing specific characteristics as capacitive charge and auxiliary net charge (not just the reverse recovery charge). These metrics are more sensitive to PTO than usual classical characteristics as reverse recovery losses or peak reverse recovery current. The Err losses confound voltage and current, and heavily depend on the integration limits. The reverse recovery peak is a good metric, but it is aliased with capacitive currents (depending on voltage slopes) and the impact of the body diode third quadrant behavior. Reducing losses in SiC-based inverters The paper “Investigation of Gate Current Shaping for SiC-based Power Modules on Electrical Drive System Power Losses” presented by speakers from German Robert Bosch and Technical University of Munich dealt with reducing the losses in SiC-based traction inverters in electric verhicles. Improving the efficiency has always been the focus of interest. The inverter power losses are mainly due to the conduction and switching losses of the power semiconductors, which depend on the output power and switching frequency. Recently, advancements on WBG materials made it possible to increase the inverter efficiency due to the superior properties of these materials. Utilizing higher switching frequencies and therefore higher voltage and current slopes brings a new challenge for gate driver’s design to make use of the superior characteristics of WBG switches. Therefore, active gate driving techniques are being adopted to be used instead of the conventional voltage source driver which provides limited control capabilities. Influencing the switching operation at every step of a switching transient could be implemented by actively adjusting the gate resistors or using an active voltage source in the driver unit. However, this control strategies are complex and provide limited degree of flexibility. One promising driving technique is based on controlling the gate current using gate current profiles. This could be achieved by either open-loop or closed-loop control. Open- loop control approaches are simple to implement and rely on a fixed profile, or an operating point dependent action. Thus, they lack the capability to react to changes in the system like manufacturing tolerances, aging effects, or temperature variations. On the other hand, closed-loop control strategies address these issues but are complex to implement and require additionally high- bandwidth sensors. Furthermore, the very fast switching behavior of WBG semiconductors makes it unfeasible to compensate the large delays observed in the feedback loop. Thus, a compromise solution would be the implementation of a scheduling technique to adapt the current profiles based on sporadic measurements of the transistors’ properties as well as the junction temperature. The different profiles are calculated offline and saved as a look-up table in the microcontroller. During operation, the microcontroller will send the control signals to an DAB topology (a) and corresponding equivalent circuit (b), neglecting the magnetizing inductance and losses