October / November 2021

www.epe2021.com EPE ECCE 2021 REVIEW 17 www.power-mag.com Issue 4 2021 Power Electronics Europe quality and reliability. Due to the higher output capacitance shape at V DS > 20 V, WBG devices will not offer clear advantages in this topology. The SiC MOSFET offers the best solution for SMPS with standard form factor and an efficiency range of 97 % to 98 %. This better efficiency is linked to the move to the Totem Pole topology and eliminates the need for bridge rectifiers. Although C OSS , Q OSS and E OSS are all higher than for the GaN transistor, the SiC device clearly benefits from a much lower increase of on-resistance over temperature. The SiC transistor is easy to drive, yet it is recommended to use a gate drive voltage of 18 V to benefit from the further lowered R DS(on) . SiC MOSFET are especially beneficial for high power applications. Solutions using GaN devices are currently capable of delivering the highest efficiencies, exceeding 98 % in standard form factor. They are the first choice for high frequency applications where the form factor is the key requirement. However, GaN solutions use a dedicated gate drive concept that requires additional effort for its implementation. GaN power devices have a strong potential for the next generation of fast-switching, high efficiency power electronics, expressed the paper “Power Cycling Results of Discrete Gallium Nitride Gate Injection Transistors” by CHEMNITZ UNIVERSITY OF TECHNOLOGY (www.tu-chemnitz.de/ etit/le/). The GIT (Gate Injection Technology) displays one very promising device concept for high voltage enhancement-mode GaN HEMTs. Beside semiconductor-level stress testing, power cycling is an important test procedure to assess the reliability of joining technologies under accelerated conditions not only for power modules but also discrete devices. Previous publications have shown that the power cycling capability of discrete GaN devices is limited by the degradation of the solder layer between housing and printed circuit board. In order to prevent PCB solder degradation during power cycling, GITs were prepared in a pressed configuration to decouple the electrical and thermal path. In this way, the focus was set on the package itself. If the package-to-PCB solder is excluded as weak point, no end-of-life criterion was reached within a reasonable scope. This demonstrates a high reliability of discrete GaN devices with nailhead-bonding technology. In this long-term investigation, the accumulated stress at constant current at the gate up to 4000 hours is significantly above the typical 1000 hours in quality tests. Furthermore, the accumulated stress by current at a temperature close to maximum allowed junction temperature is significantly above the application conditions. Reasons for the high power cycling capability is on the one hand the high number of bond wires with small diameters. On the other hand, the temperature-stress condition of the bond wires is significantly reduced due to the location at the edge of the lateral GaN chip outside the active area. Furthermore, thermal imaging shows that the junction temperature measurement using the gate diode of p-GaN GIT as TSEP is very well applicable. Power Cycling of GaN Transistors Microscope image of the chip top side after removal of the mold compound by chemical treatment; the dashed red line frames the active area Polymer-based heat dissipator for GaN transistors The paper “Investigation of 3D printed polymer-based heat dissipator for GaN transistors” presented by French Ampere Lab (www.ampere-lab.fr ) introduced a polymer-based heat-pipe evaporator for GaN transistors using AM and plastronics. GaN transistors are limited in their operational capabilities due to some limitations, of which the thermal management aspects. Until now, most of the existing heat-dissipator systems using additive manufacturing (AM) are based on a metallic finned heat sink, which is heavy and has a relatively high thermal resistance. Heat dissipation based on a phase change as operated inheat pipes is more efficient. Such heat sinks have been experimented with metals or ceramics and not by now with polymers. However, this may be of great interest. The use of polymer may enable reducing weight and cost of the thermal device. It may allow also improving the chemical compatibility of the heat pipe material and fluid, as this is often a severe issue. This paper presented a characterization of a 3D-printed polymer-based heat pipe evaporator intended for GaN transistors. The electronic copper circuit on the polymer surface is created using plastronics technology. The use of polymer for heat pipes allows reducing the weight and cost of the assembly and improving their chemical compatibility with the cooling fluid. The copper circuit receiving the electronic components, is directly fabricated on the polymer surface. The copper thickness and the electrical resistivity provide a sufficient conductivity for the circuit operation. However, the electrical conductivity could be improved using electrolytic Cu plating to adapt to high current rating. A specific test bench was developed to characterize the effective heat transfer between the polymer wall and the heat pipe working fluid. Based on the observations of the two-phase flow, a fully developed boiling regime can be achieved on this particular type of material. This allows to improve the overall thermal performance of the evaporator. Design structure details of the 3D printed and copper metallized evaporator- (a) isometric section view, (b) bottom view, (c) cross section view