June/July 2021

32 APEC 2021 www.apec-conf.org Issue 3 2021 Power Electronics Europe www.power-mag.com High-Efficient GaN-based Totem Pole Interleaved Bridgeless Bidirectional PFC more crucial under the clamped output of the switches S 1 and S 1. It requires a volume of less than four liters and targets a nominal power of 24 kW. According to the efficiency measurement of the single-phase prototype it achieves a peak efficiency of 99.2 %. In comparison to standard two-level inverter this is a reduction of nearly factor ten for the required volume while increasing the peak efficiency of the inverter from around 97 % to 99.2 %. Measurements on this three-phase prototype also at higher power points and implementation of an adequate closed loop control are part of upcoming tests. The focus of this project is on the EMI filter and the grid connected inverter. In actual standard inverters with a nominal power of 24 kW these components require a large volume of 15 - 25 liters and reach a peak efficiency around 97 %. This high volume and low efficiency is mainly based on the high EMI filter effort. In order to reduce the filter effort the switching frequency could be increased (often in combination with SiC switches) or the amplitude of the switched voltage could be reduced. A flying capacitor GaN multilevel inverter combines both aspects. The voltage steps are reduced with a rising number of voltage levels N according to. Additionally the output switching frequency is increased when Phase Shifted Pulse Width Modulation (PSPWM) is used. Therefore this topology in combination with GaN switches has huge potential to improve the efficiency and the volume of such a grid connected inverter. The first part of this project is focused on one phase (Figure 1) of the approximated minimal loop inductance of 1 nH could be achieved while still meeting the industrial guidelines on minimal clearance and creepage distances. Additional to the parasitic loop inductance a further critical effect based on parasitic components for the flying capacitor GaN multilevel layout was investigated. This effect is based on the parasitic capacitors which occur between the copper layers of the flying capacitors and the midpoint. Additional copper layer of the clamped output between the switches S 1 and ?? 1 could lead to another parasitic capacitor with the copper plane connected to the midpoint. These capacitors have the potential to build up resonance points with the parasitic inductances of connectors or large SMD capacitors. The voltage ringing which appears if such a resonance frequency is in the critical area could be measured with the first prototype and also validated by a simulation. The described phenomenon amplified the voltage Figure 1: Electrical circuit of a single-phase flying capacitor with N voltage levels and a LCLC EMI filter connected to the output grid connected inverter including the final EMI filter. This prototype will be extended by two further phases in the final design. Experimental results Based on this prototype major parasitic components where analyzed and their impact on the inverter output was investigated. This includes the precise investigation of the parasitic inductance from the commutation loop with a comparison to standard half bridge GaN designs which already achieve minimal loop inductances up to 0.25 nH. According to these investigations a flying capacitor commutation loop design with a overshoot at the switching event by nearly a factor of two. It was possible to build an improved prototype (Figure 2) with reduced parasitics which enabled a very efficient power conversion. In particular this prototype including the EMI filter achieved a peak efficiency of 99.2 % at a switching frequency of 800 kHz which is actual the highest measured efficiency at such a switching frequency and power. Therefore this prototype demonstrated the usability of flying capacitor GaN multilevel inverters also for applications with strong requirements on the inverter efficiency. These multilevel inverters enable improvements of nearly factor 10 for the overall volume and can increase the peak efficiency from 97 % towards 99.2 % in comparison to standard two-level grid connected industrial inverters. Literature Reduced Parasitics Leading to a 99.2 % Efficient Single-Phase Nine-Level Inverter at a Switching Frequency of 800 kHz, APEC 2021 Procedings, pages 809-816 Figure 2: Improved prototype with no connection to the nine-level mainboard. The resulting parasitic capacitors to the midpoint and the parasitic inductance of the SMD connectors are fully eliminated. The EMI filter of this prototype is placed on a second board and connected with a cable to the clamped output This paper by the Semiconductor Power Electronics Center (SPEC) and Infineon Technologies (USA) presented the design of a high-density GaN- based totem pole interleaved bridgeless bidirectional PFC. The bridgeless design approach and zero reverse-recovery loss characteristic of GaN allows efficient operation better than that of comparable Si-based designs. Forced air- cooling in combination with an efficient thermal design contribute to a power density exceeding 87W/inch 3 while maintaining device temperatures well below thermal limits. Infineon Technologies, El Segundo, USA (Eric.Persson@infineon.com ) Traditional PFC circuits use full-bridge diode rectifier followed by a boost stage to achieve power factor correction. The boost stage high-frequency switch is usually realized using an Si power MOSFET. Due to high conduction losses in the bridge-rectifier stage, more recent approaches use a “bridgeless” or “semi-bridgeless” approach to reduce these losses. Though this is a significant improvement, these designs still suffer from severe reverse recovery losses associated with the Si power MOSFET. The totem-pole bridgeless PFC topology (Figure 1) has not been widely adopted due to still present reverse-recovery losses of Si devices. GaN FETs are essentially free of reverse-recovery loss and present an attractive efficient alternative when used in this topology.