June/July 2021

Figure 4: Tested efficiency at 50 V output voltage www.apec-conf.org APEC 2021 31 www.power-mag.com Issue 3 2021 Power Electronics Europe integrated into one core. The converter has variable output voltage from 40 V : 60 V to charge the bus battery. Figure 4 shows the converter tested efficiency compared to the first design with four transformers and a round core shape. The proposed core design offers higher light-load efficiency thanks to the reduced core loss at 48 V output. Literature High Power Density 1 MHz 3 kW 400 V-48 V LLC Converter for Datacenters with improved Core Loss and Termination Loss, APEC 2021 Procedings, pages 304-309 Monolithic Integration of a 5 MHz GaN Half-Bridge in a 200 V GaN-on-SOI Process This awarded paper (Best Presentation) presented key building blocks of a monolithic GaN half-bridge solution - a binary-weighted digitally-controlled segmented gate-driver, offering slew-rate control; a high-voltage floating level- shifter with glitch prevention; and a monolithic half-bridge with integrated fixed-strength gate-drivers. Together, they facilitate on-chip active gate-driving, improving the reliability of GaN power ICs. Wan Lin Jiang, University of Toronto; Herbert De Vleeschouwer, ON Semiconductor, Belgium GaN’s high dv/dt can be controlled with active gate-drive methods, which has been demonstrated with Si-GaN copackaged designs. However, the limited range of allowable gate-to-source voltage in GaN HEMTs leads to a higher risk of false turn-on and device over-stress, which can be mitigated with integrated gate-drivers. The lack of p-type HEMTs in most GaN processes prevents direct migration of Si-based gate-driver designs to GaN. Moreover, the level of integration complexity is limited by the process design kits’ lower maturity level and the limited range of available passive devices and HEMT voltage ratings. On the other hand, gate-drivers with dynamically-programmable strength can limit EMI and operate reliably under different load conditions. Existing solutions for drive-strength control of monolithic GaN drivers have either used off-chip resistors, which are not dynamically controllable, or a dual-current-supply scheme, which is more amenable to analog control. Digital dv/dt control schemes, thus far unexplored in GaN ICs, provide more design flexibility and are less sensitive to process and temperature variations. GaN-on-SOI process The circuits are functionally demonstrated using three separate ICs fabricated in imec’s 200 V GaN-on-SOI process, shown in Figure 1. A deep trench isolation is used to isolate voltage domains. This process has a design kit for simulation and layout verification. A 200-V, 80-m Ω power e-HEMT with the segmented gate-driver was fabricated in the imec 200 V GaN-on- SOI process. With 200 V drain-source and 0 V gate-source voltage, the drain leakage current is 59.6 A, and drops to 1.5 A for V GS = -1 V. The GaN circuits were simulated using the MVSG-HV model for the HEMTs, producing a maximum dv DS /dt of 112 V/ns at room temperature. A single-die GaN half-bridge IC with an integrated fixed-strength gate-drive scheme is used to achieve fast and oscillation-free V DS switching performance, highlighting the benefits of monolithic integration. Finally, the potential for fast on-chip voltagelevel translation of high-frequency signals Literature Monolithic Integration of a 5-MHz GaN Half-Bridge in a 200-V GaN-on-SOI Process: Programmable dv/dt Control and Floating High-Voltage Level-Shifter, APEC 2021 Procedings, pages 728-734 Figure 1: Cross-section of imec’s 200 V GaN-on-SOI process Efficient Single-Phase Nine-Level Inverter The flying capacitor multilevel inverter is achieving highest power densities in recent power electronic devices. These positive results are based on minimal filter volumes due to effective output switching frequencies around hundreds of kilohertz up to several MHz. To achieve these high output frequencies the flying capacitor multilevel topology is crucial in addition with GaN switches. In theoretical calculations efficiencies around 99.4 % should be possible for the overall inverter at these operation conditions. These target efficiencies could not be reached yet in practical prototypes due to high commutation loop inductances and parasitic capacitances to the midpoint. This paper investigates the theoretical background of these parasitics, their effect on the inverter and presents an improved hardware implementation to verify the theoretical results. Carina Primas, Digital Industries at Siemens AG, Erlangen/Germany (carina.primas@siemens.com ) A layout of a three-phase prototype is designed according to the single- phase prototype with 800 kHz switching frequency with no copper surface underneath the switching voltage potentials of the flying capacitors and even

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