June/July 2021

www.pcim.mesago.com PCIM EUROPE 2021 21 www.power-mag.com Issue 3 2021 Power Electronics Europe degradations in the thermal path, which are more pronounced at higher ∅ Tvj. The reference modules reveal a different behavior: At common test accelerations, overlapping degradation mechanisms on the chip’s top- and bottom-side occur, yielding an increase of Rthj,c and VCE,sat as well as of ∅ Tvj, where the failure threshold of +5% VCE,sat is met due to a typical jump in VCE,sat, indicating a bond wire lift-off. Obviously, the fast power cycling tests under thermal over-load conditions reduce the test time drastically. In case of the engineering samples, the measured power cycling data derived for different temperature swings look qualitatively similar to Figure 2a for all test runs. Therefore, the same dominating failure mechanism can be expected. Micrographic analyses confirm that the intended failure mechanism has been triggered during power cycling. In Figure 3 the micrographic analysis of the engineering sample tested under thermal overload of Figure 2a is shown: At the chip edge (Figure 3a), the top-side Al-metallisation is clearly degraded, which was intended to trigger, while the sinter layer underneath the IGBT is not damaged. At the chip centre (Figure 3b), the Al-metallisation as well as the sinter layer is degraded. The latter, however, was triggered after the EOL criterion of +5% VCE,sat was reached (Figure 2a). The dominant failure mechanism is therefore clearly the degradation of the top-side Al-metallisation, which is more pronounced at the chip edge. Outlook Packaging technology becomes an even more important topic regarding wide bandgap semiconductors. To benefit from their potential, e.g. the higher switching speeds and higher possible operating temperatures on system level, low-inductive and highly reliable packages are needed. Regarding SiC MOSFETs, the much higher stiffness further challenges the chip-near interconnects, as more plastic strain is generated compared to Si during power cycling. The development of further improvements and new interconnects will obviously be accelerated with the possibility to apply rapid test- and qualification approaches. Consequently, it is aimed to extend the proposed approach for the application to SiC MOSFETs. Literature Accelerated Qualification of Highly Reliable Chip Interconnect Technology by Power Cycling Under Thermal Overload, Proceedings PCIM Europe digital days 2021, pages 1385-1392 Figure 1: Device under test: 650 V/200 A IGBT in a standard housing with copper baseplate; the highly reliable chip-near interconnect technology is highlighted Figure 3: Micrographic analysis of an engineering sample after power cycling under thermal overload; ∅ Tvj = 170 K; Tvj,m = 120°C Figure 2: Comparison of the derived normalized power cycling data obtained under thermal overload at ∅ Tvj = 170 K and a common test acceleration at ∅ Tvj = 90 K for the engineering samples and the reference modules with standard