June/July 2021

20 PCIM EUROPE 2021 www.pcim.mesago.com Issue 3 2021 Power Electronics Europe www.power-mag.com Figure 2. With this test concept it is possible to generate additional switching losses depending on the switching frequency and switching inductance Lx. In the experimental section, a total of six tests have been performed with the same Econo-style package module type. The design of experiment was carried out in a way that the first results in test 1-3 can be compared directly with standard power cycling methods due to the temperature swing up to 50 K. Nevertheless, an extreme low on-time of 10 - 20 ms is used. These test conditions were chosen because of the periodic heating, e.g. in an inverter or rectifier, which correlates with the grid frequency. For 50 Hz in a one-phase system, approx. 10 ms heating time occurs, for three phase motor drive systems this can be higher or lower. The time 10 - 20 ms was selected as compromise. The power loss density is still significantly above application level to ensure accelerated testing. For the 50 Hz half-sine application with an expected Z th,j-c (0,01s) = 0.05 K/W the worst-case temperature ripple is in the range of 13 K which leads to a PV/A of 2.5 W/mm 2 . The test results and the failure analysis showed that the failure mode for test 1 (DC-test) is bond wire lift-off (+5% V ce ). This was expected due to the high load current which was approx. 1.8 times the rated current. Test 2 and 3 show a mix between +5% V ce and +20 % R th increase. While test 2 shows a tendency to bond wire lift off, test 3 tends more towards solder layer degradation (+20% R th ). Test 4 and 5 clearly fail by solder layer degradation with a still good bond wire health state. The finished experimental results after a total of more than 250 million power cycling swings for tests 1-5 are shown in Figures 3 and 4. Literature Power Cycling Lifetime Investigation under Low Temperature Swings and 50 Hz Load with Experiment and Simulation, Proceedings PCIM Europe digital days 2021, pages 1377-1384 Figure 3: Experimental results for test 1 and 3 with CIPS reference expectation in black and modified CIPS in red for t on = 20 ms Figure 4: Experimental results for test 2, 4 and 5 with CIPS reference expectation in black and modified CIPS in red for t on = 10 ms This awarded paper (Young Engineer Award) proposes power cycling tests of engineering samples with highly reliable chip-near interconnects and commercial modules with standard interconnects for reference. The results reveal a high power cycling capability of the engineering samples - roughly ten times higher than the power cycling capability of the reference modules - which motivates to identify approaches to accelerate the EOL tests. Such an approach has been investigated by power cycling under thermal over-load conditions in combination with short load pulses, permitting to reduce the test time of chip-near interconnects from several months to one day without changing the underlying failure mechanism. Thus, the proposed approach is suitable to reduce qualification costs and time-to-market of new products and innovations drastically. Carsten Kempiak, Otto-von-Guericke-University Magdeburg, Germany (carsten.kempiak@ovgu.de) Recent highly reliable interconnect technologies like silver sintering, diffusion soldering and copper bond wires are increasingly used in power semiconductor devices. They permit to achieve a higher reliability or to operate the devices at elevated junction temperature, either resulting in a higher power density or permitting operation in harsh environments with elevated temperature. Therefore, advancing the established package qualification tests like power cycling to speed up the qualification process is highly desirable. Power cycling under thermal overload Lifetime models reveal that the lifetime of power electronic packages depends on many parameters, where the junction temperature swing has by far the biggest impact. Therefore, performing power cycling tests under thermal overload conditions to further increase the temperature swing is a promising approach to shorten the test time. For this investigation, special engineering samples with a 650 V/200 A Si IGBT in a standard housing have been built (Figure 1). The bottom side of the IGBT is sintered onto a DCB while a copper bondbuffer is sintered on its top- side, carrying eight thick copper bond wires for the emitter connection. The IGBT is rated for a maximum junction temperature of 175°C. For reference purposes, commercial modules with a similar rating (FS200R07N3E4R) and standard interconnects (thick aluminum bond wires and soldered chips) were additionally tested. Exemplary power cycling results under thermal overload condition with ∅ Tvj = 170 K and with a common test acceleration ∅ Tvj = 90 K are shown in Figure 2a for the engineering samples and in 2b for the reference modules, respectively. All of these power cycling tests were carried out at a medium junction temperature of Tvj,m = 120°C and with short load pulses of ton = 0.5 s and toff = 1.5 s. In order to observe whether the underlying degradation process has changed due to the thermal overload condition, the normalized power cycling data of each DUT is plotted together. For the engineering samples, the +5% VCE,sat failure criterion is always met first due to a continuous increase, indicating continuously growing cracks in the top-side Al-metallisation, as intended to trigger in all test runs. Also the Rthj,c data look quite similar even considering the large difference in the number of cycles to failure Nf : Rthj,c stays roughly constant until the failure threshold is met and starts to increase afterwards, indicating additional Accelerated Qualification of Highly Reliable Chip Interconnections