June/July 2021

www.pcim.mesago.com PCIM EUROPE 2021 19 www.power-mag.com Issue 3 2021 Power Electronics Europe current injection is prepared by turning Taux on. Both the value of i aux and the timing of when to push the current to the gate is decided by the on duration of Taux together with the turn-on/off instants of the switches T 1, T 3 and Taux . Thus, by adjusting the value of t aux , the magnitude of i aux and the current injection instant are configurable. This auxiliary current injection allows for a second adjustment of the gate voltage; hence a finer control of the drain-source voltage rise and fall times of the DUT and a faster/slower transition through the Miller plateau is achievable. The auxiliary turn-on completes the turn-on process with the gate voltage to be kept constant at V H by keeping T 3 on. The complete waveform of the turn-on process is shown in Figure 2. The gate-source manipulation achieved by the proposed ACSGD allows for separate control of turn-on/off delay times, di/dt and dv/dt , as well as for reduced switching loss of the device under test. The working principle is verified experimentally using a passive capacitive load imitating the input- capacitance C iss of the DUT. It has been shown experimentally that V gs can be accurately manipulated by varying the timing parameters of the drive switches. A reduction of the ?????? rise time can be reduced by 40 % and manipulated with a second current injection. Literature An Adaptive Current Source Gate Driver for SiC MOSFETs with Double Gate Current Injection, Proceedings PCIM Europe digital days 2021, pages 1271- 1277 LEFT Figure 2: Waveforms of the complete turn-on sequence This awarded paper (Young Engineer Award) focuses on the high cycle fatigue zone with low temperature swings for power modules, which is a new field in experimental testing. An advanced power cycling test concept, which can provide switching and conduction losses, was used. This combination allows accelerated testing with a load frequency of 50 Hz while avoiding to over- stress devices with a current beyond specification. A design of experiments was developed and carried out with several million power cycling swings. Unexpectedly, the results can be fitted with standard models up to temperature swings 25 K. A wide range of simulations has been performed to further investigate the temperature distribution and the mechanical background. The mechanical simulation underlined the failure analysis which exposes solder layer degradation as a main failure mode for low temperature swings. Christian Schwabe, Technische Universität Chemnitz, Germany (christian.schwabe@etit.tu-chemnitz.de ) For standard packaging technology, bond wires and solder layers are the main weak points. For these kinds of failure positions empirical lifetime models, based on a high number of samples, have been introduced. For small temperature swings, experimental data is very rare. Lifetime statistics in this range are hard to obtain, because for these test conditions a long runtime up to several years is expected. To reduce testing time, the on-time is reduced in the millisecond range. This leads to new challenges, because to generate enough losses for a suitable accelerated test, higher currents than the rated current have to be used. To circumvent this disadvantage, a new test concept was developed. Power cycling with switching losses A new test strategy based on standard power cycling topology but with a special pulse pattern was developed. It can combine the advantage of an adjustable portion of switching losses and high measurement accuracy (Figure 1). A total of three devices can be tested per phase: two devices with switching losses (DUT 1, 2) and one device with only conduction losses as reference device. The reference device is subjected to a standard power cycling test (DC-test). The load current is toggled with high frequency between the switched devices. This leads to inductive switching where the voltage is limited by a boosted active clamping circuit (BAC). A single turn-off event is shown in Power Cycling Lifetime Investigation Figure 1: Schematic circuit of power cycling switching losses with detailed phase 1 Figure 2: Single turn-off event for load current of 150 A and 250 V collector-emitter voltage