June/July 2021

10 INDUSTRY NEWS Issue 3 2021 Power Electronics Europe www.power-mag.com The uP1966E is an 85 V dual-channel gate driver designed to drive both high- side and low-side eGaN FETS in half-bridge and full-bridge topologies including DC/DC buck and boost converters, LLC DC/DC converters, buck- boost, or bidirectional converters for battery charging and motor drives. Since it is rated at 85 V the device is therefore suitable for input voltages up to 60 V and ideal to pair with EPC 80 V and 100 V FETs and integrated half-bridges. The uP1966E has split gate outputs that can operate to several MHz on both high and low side drive channels, providing the ability to adjust both turn- on and turn-off transition times independently. A clamping circuit is used on the high side drive to keep unwanted transients from damaging GaN device gates. The uP1966E has two PWM inputs that independently control high side and low side drive signals and is available in a 12-pin WLCSP package that minimizes package inductance for improved high-speed operation. Operating temperature range is -40°C to +125°C. Under-voltage protection (UVLO) When the uP1966E detects a starting threshold voltage level of 4.0V (typical) on a rising edge, the device will go from its 120 µA quiescent current state to normal operation. The uP1966E will turn off after the input falls 0.35 V below the starting threshold. A POR signal is initiated from the UVLO circuit that is used internally to assure that the output(s) will only function if the drive voltage levels are valid (~5V). PWM inputs There are two non-inverting inputs, HI and LI, that control the two output channels of the uP1966E. Provided that a POR is granted, the HI PWM input at a logic high turns on the high-side gate driver output, UGH, turns off UGL. GaN Half-Bridge EPC and Taiwan-based uPI Semiconductor are partnering to offer the uP1966 GaN half-bridge. The driver integrates an internal bootstrap supply and UVLO in a small 1.6 mm x 1.6 mm WLCSP form factor. When the HI PWM input goes low the high-side gate driver output, UGL, and turns on, UGH turns off. The LI PWM input at a logic high turns on the low-side gate driver output, LGH, turns off LGL. When the LI PWM input goes low the low-side gate driver output, LGL, and turns on, LGH turns off. There is no lockout between HI and LI inputs: both GaN devices can be driven on at the same time. If these inputs are not used they should be tied to ground. Although there is a 200 k Ω resistor to ground on each PWM input under no circumstances should either of these inputs be allowed to float. Figure 3 shows the typical operation of the PWM input in a synchronous regulator application. LI turns off, add delay time (a “dead time”) determined by external control then HI turns on. In reverse, HI turns off, add a delay time, and then LI turns on. The minimum delay time of 30 ns is recommended for operation application. High-side driver The high-side driver is designed to “float” meaning that its reference (ground) floats with the PHASE pin of the uP1966E which is normally tied to the source of an N-channel GaN FET. The bias voltage to the high-side driver is supplied to the BOOT pin through a bootstrap switch (diode) see Figure 4, so that a ABOVE Figure 1: Functional block diagram of he uP1966E GaN driver RIGHT Figure 2: Typical application circuit. It is important that the decoupling capacitor, CVCC, be returned directly to the ground pin, A2. CVCC should be a 1µF MLCCs. An X7R dielectric is recommended. The loop comprised of CBOOT and RBOOT should be as short as possible Figure 3: PWM input timing diagram Figure 4: Bootstrap switch circuit